Timing recovery is a very important receiver function for DMT-based VDSL2 systems. It is vital to design a good timing recovery system to suppress the jitter noise to a level that is comparable to the receiver noise in the loop. Otherwise, the receiver performance will be limited by the poor timing recovery response. In DMT-based systems, single or multiple frequency tones are used as pilot tones that embed the timing phase signals. The timing recovery module reconstructs the phase information from the pilot tones, which is used as reference to the timing recovery control loop. The timing recovery control loop produces frequency control signal to adjust the local clock frequency correspondingly to match the transmitter system clock. In order to achieve superior performance, it is important to reconstruct high-accurate phase information from the pilot tones.
In VDSL2 systems, timing recovery or clock recovery is always a basic building block. Usually the transceivers at the central office drive the DAC signal out and sample the ADC data at a local crystal oscillator. At the customer premise, the transceiver also drives out the DAC signal and samples ADC signal at a local clock. It is impossible to have the exactly same crystal oscillator frequency on both the central office and the customer premises. Therefore, timing recovery system is utilized at the customer premise to recovery the clock information so that effectively the transceivers on both sides have the same clock frequency.
Timing recovery systems usually consist of the phase detection module and the second-order control loop. From the received signal, the phase detection module retrieves the clock frequency information that is embedded by the transceivers on the central office. The clock frequency information is basically related to the clock frequency difference between the master clock on the central office and the slave clock on the customer premises. The frequency difference is then used to drive the second-order control loop to adjust the slave clock through the voltage-controlled crystal oscillator (VCXO) or digitally-controlled crystal oscillator (DCXO). With the communication channel as a part of the closed-loop system, the frequency difference eventually will be driven to zero which means that the slave clock on the customer premise has the same clock frequency as the master clock on the central office.
The timing recovery system design shall be considered an integrated part of the transceiver communication systems. An over-designed system could waste the system cost including hardware and firmware. An under-designed system could limit the overall system performance. One important factor that affects the timing recovery system performance is the measurement noise. The measurement noise comes primarily from the crosstalk, RF interference, and board AWGN. For a single pilot tone scheme, the performance will significantly deteriorate if the measurement noise on the chosen pilot tone suddenly becomes worse due to new noise source. With single pilot tone scheme, the modem may have to go to retrain in order to choose another pilot tone so that the system performance will not be limited by the clock jitter noise. However, if multiple pilot tones are used, the adaptation scheme running on the hardware or firmware can quickly pick up the affected tone and limit its deteriorating effect by reducing its corresponding weight. Therefore, the performance can be maintained and the modem does not necessarily go to retrain.
On the other hand, the phase estimation itself could affect the system performance. Usually in a DMT-based system, the phase estimation is extracted from the FFT outputs for the selected pilot tones, which are basically complex vector with real and imaginary values. The phase estimation module needs to reconstruct the phase information from those real and imaginary values. How accurate is the phase estimation also significantly affects the overall system performance.